CDVP :: HARDWARE SUBGROUP
 Dublin City University, Ireland
 
Val Muresan
Dr. Valentin (Val) Muresan
EEng, MBA, PhD, MIEE, MIEEE

Val's Publications before he joined CDVP and other Technical Reports

  1.       Greedy Tree Growing Heuristics on Block-Test Scheduling under Power Constraints, V. Muresan, X. Wang, V. Muresan, M. Vladutiu, Journal of Electronic Testing: Theory and Applications, Vol 20, pages 61-78, 2004.

     

  2.       Power-Efficient Hardware Accelerators for MPEG-4 Mobile Multimedia Platforms, V. Muresan, Deliverable Report, Video Media Processing Group, Centre for Digital Video Processing, DCU, April 2003.

     

  3.       Hardware Acceleration Architectures for MPEG-based Mobile Video Platforms: A Brief Overview, N. O’Connor, V. Muresan, A. Kinane, D. Larkin, S. Marlow, N. Murphy, 4th European Workshop on Image Analysis for Multimedia Interactive Services, London, UK, April 2003.

     

  4.       Hardware Acceleration Architectures for MPEG-based Mobile Video Platforms: An Overview, V. Muresan, A. Kinane, D. Larkin, Technical Report, Video Media Processing Group, Centre for Digital Video Processing, DCU, Jan 2003.

     

  5.       Power Management for MPEG-4 Peripherals Targeted to Mobile Multimedia Platforms, V. Muresan, N. O’Connor, N. Murphy, S. Marlow, Technical Report, Video Media Processing Group, Centre for Digital Video Processing, DCU, May 2002.

     

  6.       Low Power Techniques for Video Compression, Valentin Muresan, Noel O’Connor, Noel Murphy, Sean Marlow, Stephen McGrath, Irish Signals and Systems Conference, Cork, Ireland, June 25-26, 2002.

     

  7.       Power-Efficient Hardware Accelerators for MPEG-4 Mobile Multimedia Platforms, V. Muresan, N. O’Connor, N. Murphy, S. Marlow, Cost 211 meeting, DCU, April 2002.

     

  8.       Fast Power-Efficient Block-Matching Structure for Motion Estimation, V. Muresan, Technical Report, Video Media Processing Group, Centre for Digital Video Processing, DCU, December 2001.

     

  9.       Low-Power Motion Estimation Techniques for Video Compression, V. Muresan, Technical Report, Video Media Processing Group, Centre for Digital Video Processing, DCU, June 2001.

     

  10.   Hardware Acceleration Solutions for Mobile Platforms, V. Muresan, Technical Report, Video Media Processing Group, Centre for Digital Video Processing, DCU, April 2001.

     

  11.   Mixed Classical Scheduling Algorithms and Tree Growing Technique in Block-Test Scheduling under Power Constraints, V. Muresan, X. Wang, V. Muresan, M. Vladutiu, Proceedings of the 12th IEEE Workshop on Rapid System Prototyping, Monterey, California, USA, June 25 - 27, 2001.

     

  12.   A Combined Tree Growing Technique For Block-test Scheduling Under Power Constraints, V. Muresan, X. Wang, V. Muresan, M. Vladutiu, Proceedings of the IEEE International Symposium on Circuits and Systems, Sydney, Australia, May 6 - 9, 2001.

     

  13.   The VHDL Model of a Three Stage ATM Switch Featuring a Cell-Level Path Allocation Algorithm, T. Khadir, V. Muresan, M. Collier, X. Wang, Proceedings of IASTED International Conference on Applied Informatics (AI2001). Innsbruck, Austria, 19-22 February 2001. pp.235-241.

     

  14.   Distribution-Graph Based Approach and Extended Tree Growing Technique in Power-Constrained Block-Test Scheduling, V. Muresan, X. Wang, V. Muresan, V. Muresan, M. Vladutiu, Proceedings of The IEEE Asian Test Symposium, Taipei, Taiwan, Dec 4 - 6, 2000.

     

  15.   The Left Edge Algorithm and the Tree Growing Technique in Block-Test Scheduling under Power Constraints, V. Muresan, X. Wang, V. Muresan, M. Vladutiu, Proceedings of The IEEE VLSI Test Symposium, Montreal, Canada, April 30 - May 4, 2000.

     

  16.   The Left Edge Algorithm in Block Test Scheduling under Power Constraints, V. Muresan, X. Wang, V. Muresan, M. Vladutiu, Proceedings of The IEEE Symposium on Circuits and Systems, Geneva, Switzerland, May 28 - May 31, 2000.

     

  17.   List Scheduling and Tree Growing Technique in Power-Constrained Block-Test Scheduling, V. Muresan, X. Wang, V. Muresan, M. Vladutiu, Proceedings of The IEEE European Test Workshop, Cascais, Portugal, May 23-26, 2000.

     

  18.   Power-Constrained Block-Test List Scheduling, V. Muresan, X. Wang, V. Muresan, M. Vladutiu, Proceedings of The IEEE International Workshop on Rapid System Prototyping, Paris, France, 21-23 June 2000.

     

  19.   A Comparison of Classical Scheduling Approaches in Power-Constrained Block-Test Scheduling, V. Muresan, X. Wang, V. Muresan, M. Vladutiu, Proceedings of The IEEE International Test Conference, Atlantic City, USA, 3-5 October 2000.

     

  20.   Design and Implementation of a Didactic Test System for FPGA Devices, V. Muresan, X. Wang, V. Muresan, M. Vladutiu, Proceedings of The Third International Conference on Technical Informatics, Timisoara, Romania, October, 1998, "Politehnica" University of Timisoara.

     

  21.   ASIC Design of a Fuzzy Logic Controller, V. Muresan, X. Wang, J.J. Yan, Proceedings of The IASTED International Conference on Control and Applications, Hawaii, USA, 1998, 12-14 August.

     

  22.   ASIC Design of an ATM Switch Featuring Multichannel Bandwidth Allocation, V. Muresan, N. Nicolici and X. Wang, Proceedings of The Second International Conference and Exhibition on Information Infrastructure, Beijing, China, 1998, April, Beijing University of Post and Telecommunications, China.

     

  23.   From VHDL to FPGA. A Case Study of a Fuzzy Logic Controller, V. Muresan, D. Crisu, X. Wang, Proceedings of The Summer International Conference of Young Lecturers and PhD Students, Miskolc, Hungary, 1997, 7-15 August, University of Miskolc.


Hardware Group
We research and develop low-power hardware accelerators for future multimedia platforms and mobile Internet
Hardware Group Contact Point
Dr. Noel O'Connor email: noel.oconnor@eeng.dcu.ie

Telephone:
+353-1-7005078

Fax:
+353-1-7005508

Address:
Centre for Digital Video Processing,
Dublin City University,
Glasnevin, Dublin 9
Ireland


CDVP::HW Group is a beneficiary of several University Programmes:


Synopsys

Synplicity

Arm

Xilinx
 
 
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© CENTRE FOR DIGITAL VIDEO PROCESSING, DUBLIN CITY UNIVERSITY 2006